Salary
We offer employees a competitive and comprehensive compensation package.
Reliable original manufacturerAs a leading Chinese manufacturer of IoT chips, HOPERF offers its employees competitive cash compensation packages and long-term and short-term incentive mechanisms. In addition to statutory national benefits, HOPERF also provides a diverse range of employee care programs.
1. Responsible for software development, debugging, testing, and certification of LoRa/Sub-1GHz (433/868/915MHz) products.
2. Develop embedded software based on conventional MCU chips and wireless RF chips.
3. Write, organize, archive, and submit software development documents for LoRa/Sub-1GHz products.
4. Complete other tasks assigned by superiors.
1. Over 3 years of experience in software development, debugging, testing, and certification of LoRa/Sub-1GHz products.
2. Proficient in using conventional development tools and languages such as Keil/IAR and C.
3. Proficient in using conventional testing equipment, including spectrum analyzers, network analyzers, signal generators, logic analyzers, oscilloscopes, and more.
4. Familiar with software driver development and application programming for RF chips such as Semtech's SX1276/1278/1262/1268, ASR6501/6505/6601, and Silicon Labs' SI4463/4431/4010.
• Competitive international compensation package.
• Assistance in applying for subsidies for eligible candidates.
• Cover letter
• Resume in both Chinese and English, including a list of academic achievements
• Please send the above materials to the recruitment email address: hr01@hoperf.com
1.Based on schematic diagrams provided by analog circuit design engineers, responsible for analog and RF layout design and verification.
2.Responsible for top-level digital and analog layout integration in chip mixed-signal designs.
3.Collaborate closely with analog circuit design engineers, engage in detailed communication, and work together to complete Design Rule Check (DRC), Layout vs. Schematic (LVS), post-layout simulation, and optimize layouts.
4.Evaluate and test Reference Designs and IPs provided by the foundry and prepare relevant documentation.
1.Bachelor's degree or higher in electronics/microelectronics or related field, with over 5 years of experience in analog layout design.
2.Proficiency in layout design and verification tools such as Virtuoso/Calibre, familiarity with the layout design and tapeout processes for mixed-signal chips, and understanding of layout DRC and LVS verification processes.
3.Ability to interpret documents provided by the foundry, such as design rules, and design layouts accordingly.
4.Strong teamwork skills, proactive attitude, ability to collaborate with layout engineers for floor planning, DRC checks, LVS verification, parasitic parameter extraction, and post-layout simulations.
5.Prior experience in analog RF module layout design, including PLL, ADC, DAC, OSC, CHP, LDO, filter, LNA, is a plus.
6.Experience in design with process nodes of 40nm or lower is preferred.
7.Prior experience in mass production of mixed-signal chips is a plus.
• Competitive international compensation package
• Assistance in applying for subsidies for eligible candidates
• Cover letter
• Resume in both Chinese and English, including a list of academic achievements
• Please send the above materials to the recruitment email address: hr01@hoperf.com
1.Responsible for top-level or IP verification of SOC chips, behavioral-level modeling.
2.Collaborate with design personnel to define verification specifications and test plans, and establish a verification platform based on UVM (Universal Verification Methodology).
3.Execute verification plans, write test cases, conduct recursive testing, and perform debugging and issue resolution.
4.Conduct gate-level functional and timing simulations.
5.Capable and interested in participating in chip design and development.
1.3-10 years of IC verification experience, with a background in microelectronics, computer science, or related fields, and a bachelor's degree or higher.
2.Familiar with IC verification processes, with extensive experience in IP/SOC verification and successful chip tape-outs.
3.Proficient in UVM verification methodology.
4.Familiar with bus protocols such as ARMAXI, APB, and AHB.
5.Familiar with common peripherals like I2C, UART, SPI, USB.
6.Proficient in C programming.
7.Prior experience in mixed-signal simulation is a plus.
• Competitive international compensation package.
• Assistance in applying for subsidies for eligible candidates.
• Cover letter.
• Resume in both Chinese and English, including a list of academic achievements.
• Please send the above materials to the recruitment email address: hr01@hoperf.com.
1. Responsible for the design of wireless MCUs and SOCs based on ARM/RISC-V cores.
2. Complete the design of SPI Flash and eFlash controllers.
3. Optimize instruction fetch efficiency and power consumption using Cache.
4. Responsible for the design and verification of digital peripherals.
5. Participate in logic synthesis, formal verification, and static timing analysis of digital circuits.
6. Participate in FPGA verification of digital circuits.
7. Prepare design documents and contribute to the development of product-related documentation.
1. More than 8 years of experience in digital circuit design.
2. Involvement in at least 5 successful tape-outs.
3. Strong fundamentals in digital circuit design, proficient in using Verilog for design.
4. Proficiency in using EDA tools from Cadence or Synopsys.
5. Familiarity with AHB and APB buses.
6. Some knowledge of low-power design.
7. Basic understanding of embedded software.
8. Excellent communication and collaboration skills.
9. Experience in wireless MCU/SOC development is a plus.
• Competitive international compensation package.
• Assistance in applying for subsidies for eligible candidates.
• Cover letter.
• Resume in both Chinese and English, including a list of academic achievements.
• Please send the above materials to the recruitment email address: hr01@hoperf.com.
1. Complete circuit modeling, design, and simulation verification, and write integrated circuit design documents.
2. Plan layout design and guide layout design engineers in implementing analog circuit layouts.
3. Write product test specifications, independently or in collaboration with test engineers to develop test plans and conduct testing of analog chips.
4. Design and develop analog circuit modules such as bandgap, operational amplifiers, ADC, DAC, etc.
5. Prepare relevant technical documents.
1. Master's degree or higher in a microelectronics-related field, with 3 years of experience in analog circuits.
2. Strong foundational knowledge in analog circuit design, with a deep understanding of operational amplifiers, voltage references, ADC, DAC, etc.
3. Proficient in using software tools such as Cadence and MATLAB for analog circuit design.
4. Proficient in using MATLAB for modeling and simulation.
5. Independently or collaboratively participated in the design of analog chips or analog circuit modules within chips (e.g., OPA, Comp, OSC, LDO, DC/DC, PLL, ADC, DAC).
6. Preference given to those with experience in power management chips and high-precision ADC and DAC design.
• Competitive international compensation package.
• Assistance in applying for subsidies for eligible candidates.
• Cover letter.
• Resume in both Chinese and English, including a list of academic achievements.
• Please send the above materials to the recruitment email address: hr01@hoperf.com.
